Reflections on a SER-aware design flow

Single Event Effects (SEEs) may cause system downtime, data corruption and maintenance incidents. Thus, the SEE are a threat to the overall system reliability, causing designers to be increasingly concerned about the analysis and the mitigation of radiation-induced failures, even for commercial systems performing in a natural working environment. Experts and reliability engineers are called in to support chip designers in the management of Single Event Effects. To this goal, we present a design-flow-oriented Soft Error Rate analysis methodology geared to allow practical and concrete decisions concerning implementation, design and functional choices in order to minimize SEEs impact on circuit and system behavior.