A 16-bit microprocessor-based digital filter architecture

Advances in integrated circuit technology have made real time digital filtering hardware a viable alternative to more conventional analog approaches. For example, an architecture to be described is currently being used as a dealiasing/interpolating FIR filter for speech acquisition/playback at 10kHz. The intent of the design is flexibility, simplicity, and ultimate low-cost. Flexibility and quantization accuracy are achieved by using a 16-bit microprocessor (Texas Instruments 9900). Simplicity as well as high speed is derived through the use of a hardware arithmetic unit featuring a TRW multiplier or multiplier/accumulator chip. Furthermore, synchronous programming and memory-mapped I/O are used to maximize thruput. With this combination of off-the shelf LSI devices, an FIR digital filter with a multiply-add rate of 160,000/second has been constructed. By design, only the instruction rate of the microprocessor limits the processing speed. Thus, as faster microprocessors become available, it is felt that this architecture will offer an inexpensive, digital alternative for many more signal-processing applications. In this paper, we describe the criteria for design, some of the alternatives, and the resulting hardware/software system.