DocumentCode :
3030447
Title :
Smart power IC simulation of substrate coupled current due to majority and minority carriers transports
Author :
Conte, Fabrizio Lo ; Sallese, Jean-Michel ; Kayal, Maher
Author_Institution :
Electron. Lab., Ecole Polytech. Fed. de Lausanne (EPFL), Lausanne, Switzerland
fYear :
2010
fDate :
2-4 June 2010
Firstpage :
168
Lastpage :
171
Abstract :
This paper presents a new approach for substrate parasitic current simulation in smart power integrated circuit. A new compact modeling approach developed in previous work has been used to create an equivalent substrate schematic. The latter is composed of new components having the peculiarity not to fully recombine minority carrier at their boundary. By the interconnection of these special components in the electrical design, the effect of substrate current is simulated. Having this information early in the design phase will allow design optimization and reduce the risk of costly chip redesign.
Keywords :
integrated circuit design; optimisation; power integrated circuits; simulation; substrates; design optimization; majority carriers transports; minority carriers transports; parasitic current simulation; smart power integrated circuit simulation; substrate coupled current; CMOS technology; Circuit simulation; Coupling circuits; Integrated circuit modeling; Integrated circuit noise; Integrated circuit technology; Low voltage; Power integrated circuits; Semiconductor device noise; Substrates; Integrated circuit modeling; power parasitic modeling; power semiconductor devices; substrate modeling; switching noise coupling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
IC Design and Technology (ICICDT), 2010 IEEE International Conference on
Conference_Location :
Grenoble
Print_ISBN :
978-1-4244-5773-1
Type :
conf
DOI :
10.1109/ICICDT.2010.5510262
Filename :
5510262
Link To Document :
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