A fixed point of DFT/FFT for FPGA platform

Author

Xu, Qi ; Duan, ZheMing

Author_Institution

Dept. of Electron. Eng., Northwestern Polytech. Univ., Xi´´an, China

Volume

1

fYear

2012

fDate

25-27 May 2012

Firstpage

279

Lastpage

282

Abstract

In this paper, the Pipelined Streaming butterfly stage of DFT/FFT is designed including CORDIC and complex algorithm to increase the Performance. This butterfly stage is full use of the register of DSP to transform the complex quantity to the simple Pipelined algorithm and the iteration of CORDIC to compute the trigonometric. The butterfly stage not only save the resources, but also increase the accuracy of result. The simulation show that the butterfly stage is highly the efficiency of compute, accuracy and range.

Keywords

computational geometry; digital signal processing chips; discrete Fourier transforms; fast Fourier transforms; field programmable gate arrays; fixed point arithmetic; iterative methods; logic design; CORDIC iteration; DFT-FFT fixed point; DSP register; FPGA platform; discrete Fourier transform; fast Fourier transform; pipelined streaming butterfly stage; trigonometric computation; Algorithm design and analysis; Digital signal processing; Discrete Fourier transforms; Field programmable gate arrays; Quantization; Random access memory; Vectors; CORDIC algorithm; butterflies; formatting DFT/FFT;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Science and Automation Engineering (CSAE), 2012 IEEE International Conference on

Conference_Location

Zhangjiajie

Print_ISBN

978-1-4673-0088-9

Type

conf

DOI

10.1109/CSAE.2012.6272597

Filename

6272597