DocumentCode
3030666
Title
Narrowing the margins with elastic clocks
Author
Cortadella, Jordi ; Lavagno, Luciano ; Amiri, Djavad ; Casanova, Jonàs ; Macián, Carlos ; Martorell, Ferran ; Moya, Juan A. ; Necchi, Luca ; Sokolov, Danil ; Tuncer, Emre
Author_Institution
Univ. Politec. de Catalunya, Barcelona, Spain
fYear
2010
fDate
2-4 June 2010
Firstpage
146
Lastpage
150
Abstract
The continuous shrinking of process geometries increases variability and demands for conservative margins that have a negative impact on performance. With conventional clocks, the cycle period has to be defined to accommodate the worst-case variations during the lifetime of the circuit. Elastic Clocks arise as a new paradigm to reduce the margins without sacrificing robustness. Their cycle-by-cycle adaptation to static and dynamic variability enables the use of reduced margins that only need to cover the differential variability of the circuit delays with regard to the elastic period. Given the substantial spatio-temporal correlation within every die, a significant reduction in the margins required to cover process variability, voltage and temperature fluctuations and aging can be achieved.
Keywords
clocks; delay circuits; integrated circuit manufacture; aging; circuit delay; circuit lifetime; cycle period; cycle-by-cycle adaptation; die; differential variability; dynamic variability; elastic clocks; elastic period; process geometry; process variability; spatio-temporal correlation; static variability; temperature fluctuation; voltage fluctuation; Aging; Circuits; Clocks; Costs; Delay; Frequency synchronization; Manufacturing processes; Registers; Testing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
IC Design and Technology (ICICDT), 2010 IEEE International Conference on
Conference_Location
Grenoble
Print_ISBN
978-1-4244-5773-1
Type
conf
DOI
10.1109/ICICDT.2010.5510273
Filename
5510273
Link To Document