DocumentCode
3030926
Title
The power7TM processor SoC
Author
Wendel, Dieter ; Kalla, Ronald ; Friedrich, Joshua ; Kahle, James ; Leenstra, Jens ; Lichtenau, Cedric ; Sinharoy, Balaram ; Starke, William ; Zyuban, Victor
fYear
2010
fDate
2-4 June 2010
Firstpage
71
Lastpage
73
Abstract
Introducing POWER7™ the latest member of the IBM POWER™ processor family. A 567 mm2 chip implemented in 45nm SOI technology, holding eight quad threaded cores, a 32MB shared eDRAM L3, two memory controllers and high bandwidth SMP interfaces. The new out of order, shallow pipeline core with 12 execution units, multiport L1 caches and a private 256 kB L2 offers the efficiency to support 4× the number of cores within the same power envelope as its predecessor. Supporting over 4 GHz, the L1 data cache loop is kept to 2 cycles. Data from the L2 can be returned to the core at a rate of 32 B per cycle.
Keywords
DRAM chips; cache storage; microprocessor chips; silicon-on-insulator; system-on-chip; IBM POWER processor family; L1 data cache loop; L2 data cache; Power7 processor; SMP interfaces; SOI technology; SoC; memory controllers; memory size 32 MByte; multiport L1 caches; quad threaded cores; shallow pipeline core; shared eDRAM L3; size 45 nm; CMOS technology; Clocks; Control systems; Frequency; Logic devices; Power distribution; Random access memory; Subthreshold current; Voltage; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
IC Design and Technology (ICICDT), 2010 IEEE International Conference on
Conference_Location
Grenoble
Print_ISBN
978-1-4244-5773-1
Type
conf
DOI
10.1109/ICICDT.2010.5510286
Filename
5510286
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