450 MHz 1.0 V to 1.8 V bidirectional mixed-voltage I/O buffer using 90-nm process

Author

Wang, Chua-Chin ; Kuo, Ron-Chi ; Liu, Jen-Wei

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

fYear

2010

fDate

2-4 June 2010

Firstpage

55

Lastpage

58

Abstract

A 1.0 V to 1.8 V mixed-voltage I/O buffer implemented with 90-nm 1-V standard CMOS devices is proposed. By using a dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit 2×VDD voltage level signal without any gate-oxide overstress hazard. Besides, the leakage current is eliminated by adopting a floating N-well circuit. The maximum data rate is simulated to be 340 MHz and 450 MHz for 1.8 V and 1.0 V, respectively, with a given capacitive load of 20 pF.

Keywords

CMOS integrated circuits; buffer circuits; bidirectional mixed-voltage I/O buffer; frequency 450 MHz; gate-oxide overstress hazard; size 90 nm; standard CMOS devices; voltage 1.0 V to 1.8 V; voltage level signal; CMOS integrated circuits; CMOS process; CMOS technology; Detectors; Diodes; Energy consumption; Leakage current; Logic; Signal generators; Voltage control; I/O buffer; floating N-well circuit; gate-oxide reliability; mixed-voltage-tolerant;

fLanguage

English

Publisher

ieee

Conference_Titel

IC Design and Technology (ICICDT), 2010 IEEE International Conference on

Conference_Location

Grenoble

Print_ISBN

978-1-4244-5773-1

Type

conf

DOI

10.1109/ICICDT.2010.5510290

Filename

5510290