A high reliable SOC on-board computer based on Leon3

Author

Pei, Luo ; Jian, Zhang

Author_Institution

Lab. of Integrated Space Electron. Technol., Center for Space Sci. & Applic. Res., Beijing, China

Volume

1

fYear

2012

fDate

25-27 May 2012

Firstpage

360

Lastpage

363

Abstract

This paper presents the design of a high reliable system-on-chip (SOC) computer system based on Leon3 processor core. The reconfigurable system is implemented on the FPGA platform and has the merit of high reliability. This article describes how the target SOC target platform was designed and the way to realize the Leon3 system on the target platform. While the SRAM-based FPGAs are very sensitive to single event upsets (SEU) effects, scrubbing and Triple Module Redundancy (TMR) were also implemented in this design to improve the reliability of the SOC system.

Keywords

SRAM chips; field programmable gate arrays; integrated circuit design; integrated circuit reliability; logic design; microprocessor chips; reconfigurable architectures; system-on-chip; FPGA platform; Leon3 processor core; Leon3 system; SEU effect; SOC on-board computer; SOC system reliability; SOC target platform; SRAM-based FPGA; TMR; reconfigurable system; scrubbing; single event upset; system-on-chip computer system; triple module redundancy; Field programmable gate arrays; Integrated circuit reliability; Registers; Reliability engineering; System-on-a-chip; Tunneling magnetoresistance; Leon3; SOC; reliability; scrubbing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Science and Automation Engineering (CSAE), 2012 IEEE International Conference on

Conference_Location

Zhangjiajie

Print_ISBN

978-1-4673-0088-9

Type

conf

DOI

10.1109/CSAE.2012.6272615

Filename

6272615