SOI digital CMOS VLSI-a design perspective

Author

Chuang, C.T. ; Puri, R.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1999

fDate

1999

Firstpage

709

Lastpage

714

Abstract

This paper reviews the recent advances of SOI for digital CMOS VLSI applications with particular emphasis on the design issues and advantages resulting from the unique SOI device structure. The technology/device requirements and design issues/challenges for high-performance, general-purpose microprocessor applications are differentiated with respect to low-power portable applications. Particular emphases are placed on the impact of floating-body in partially-depleted devices on the circuit operation, stability, and functionality. Unique SOI design aspects such as parasitic bipolar effect and hysteretic V_T variation are addressed. Circuit techniques to improve the noise immunity and global design issues are discussed

Keywords

CMOS digital integrated circuits; VLSI; circuit stability; integrated circuit design; low-power electronics; reviews; silicon-on-insulator; SOI digital CMOS VLSI; Si; circuit stability; design issues; floating-body effect; hysteretic V_T variation; low-power portable applications; microprocessor applications; noise immunity; parasitic bipolar effect; partially-depleted devices; threshold voltage variation; CMOS technology; Circuit noise; Circuit stability; Hysteresis; Microprocessors; Permission; Semiconductor films; Silicon germanium; Silicon on insulator technology; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1999. Proceedings. 36th

Conference_Location

New Orleans, LA

Print_ISBN

1-58113-092-9

Type

conf

DOI

10.1109/DAC.1999.782045

Filename

782045