Fully depleted Silicon-On-Insulator with back bias and strain for low power and high performance applications

We demonstrate that planar Fully Depleted Silicon-On-Insulator (FDSOI) architectures allow improving the electrostatic control (and in turn the dynamic performance by 22%) and the variability of Complementary Metal-Oxide-Semiconductors (CMOS) devices, compared to the bulk technology. It is thus an ideal solution for Low Power (LP) applications and SRAM stability at the 22 nm node and below. Moreover, integrated on both Ultra-Thin Body and Buried oxide (UTB²), it enables the use of standard power management technique (Reverse Back or Source Biasing) with a high efficiency. Finally, some technological options exist in order to boost its ON-state current (I_ON) like strained SOI substrates for nMOS and embedded SiGe source/drain for pMOS.