DocumentCode
3031111
Title
A low power NORA circuit design technique based on charge recycling
Author
Tsiatouhas, Y. ; Limniotis, K. ; Arapoyanni, A. ; Haniotakis, Th
Author_Institution
Dept. of Comput. Sci., Ioannina Univ., Greece
Volume
1
fYear
2003
fDate
14-17 Dec. 2003
Firstpage
224
Abstract
In this paper we present a low power oriented design technique for NORA clocked circuits. This technique is based on a new switching scheme for charge recycling among circuit nodes. According to our approach and the corresponding simulations in a 0.18μm CMOS technology, a maximum energy dissipation reduction of 19 % is reported while energy*delay product savings up to 14 % can be achieved.
Keywords
CMOS logic circuits; circuit simulation; integrated circuit design; logic CAD; logic simulation; low-power electronics; CMOS technology; NORA clocked circuits; SPECTRE simulations; charge recycling; circuit nodes; dynamic logic networks; energy delay product savings; low power oriented design technique; maximum energy dissipation reduction; switching scheme; CMOS technology; Circuit simulation; Circuit synthesis; Clocks; Energy dissipation; Leakage current; Pulse inverters; Recycling; Switching circuits; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on
Print_ISBN
0-7803-8163-7
Type
conf
DOI
10.1109/ICECS.2003.1302017
Filename
1302017
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