Title :
Analysis of performance impact caused by power supply noise in deep submicron devices
Author :
Jiang, Yi-Min ; Cheng, Kwang-Ting
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Abstract :
The paper addresses the problem of analyzing the performance degradation caused by noise in power supply lines for deep submicron CMOS devices. We first propose a statistical modeling technique for the power supply noise including inductive ΔI noise and power net IR voltage drop. The model is then integrated with a statistical timing analysis framework to estimate the performance degradation caused by the power supply noise. Experimental results of our analysis framework, validated by HSPICE, for benchmark circuits implemented on both 0.25 μ, 2.5 V and 0.55 μ, 3.3 V technologies are presented and discussed. The results show that on average, with the consideration of this noise effect, the circuit critical path delays increase by 33% and 18%, respectively for circuits implemented on these two technologies
Keywords :
CMOS integrated circuits; SPICE; VLSI; circuit simulation; delays; integrated circuit modelling; integrated circuit noise; power supply circuits; statistical analysis; timing; 0.25 micron; 0.55 micron; 2.5 V; 3.3 V; CMOS devices; HSPICE; benchmark circuits; circuit critical path delays; deep submicron devices; inductive noise; performance degradation; performance impact; power net IR voltage drop; power supply lines; power supply noise; statistical modeling technique; statistical timing analysis framework; Circuit noise; Degradation; Integrated circuit interconnections; Noise level; Performance analysis; Power supplies; Probability density function; Propagation delay; Timing; Voltage;
Conference_Titel :
Design Automation Conference, 1999. Proceedings. 36th
Conference_Location :
New Orleans, LA
Print_ISBN :
1-58113-092-9
DOI :
10.1109/DAC.1999.782118
