A low-power sub-nanosecond standard-cells based adder

This paper presents a new standard-cells based low-power subnanosecond 64-bit adder. For the first time, in the proposed circuit, a hybrid quaternary carry-look-ahead carry-skip tree is exploited to quickly compute carries into appropriate positions. Moreover, sum units organized as carry-increment blocks are used. When realized with the standard-cell libraries of the ST 0.18 μm 1.8 V CMOS technology, the new adder exhibits a computational delay of just 980 ps, an average power dissipation of 27 mW at 500 MHz and a silicon area occupancy of about 0.015 mm².