A low-power sub-nanosecond standard-cells based adder

Author

Perri, Stefania ; Corsonello, Pasquale ; Staino, Giovanni

Author_Institution

Dept. of Electron., Comput. Sci. & Syst., Univ. della Calabria, Rende, Italy

Volume

1

fYear

2003

fDate

14-17 Dec. 2003

Firstpage

296

Abstract

This paper presents a new standard-cells based low-power subnanosecond 64-bit adder. For the first time, in the proposed circuit, a hybrid quaternary carry-look-ahead carry-skip tree is exploited to quickly compute carries into appropriate positions. Moreover, sum units organized as carry-increment blocks are used. When realized with the standard-cell libraries of the ST 0.18 μm 1.8 V CMOS technology, the new adder exhibits a computational delay of just 980 ps, an average power dissipation of 27 mW at 500 MHz and a silicon area occupancy of about 0.015 mm².

Keywords

CMOS logic circuits; adders; carry logic; logic design; low-power electronics; 0.18 micron; 1.8 V; 27 mW; 500 MHz; 64 bit; 980 ps; CMOS technology; carry-increment block sum units; carry-look-ahead; computational delay; hybrid quaternary carry-skip tree; low-power adder; standard-cells based adder; subnanosecond adder; Adders; CMOS technology; Circuits; Computer science; Lab-on-a-chip; Mathematics; Power dissipation; Silicon; Software libraries; Transportation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on

Print_ISBN

0-7803-8163-7

Type

conf

DOI

10.1109/ICECS.2003.1302035

Filename

1302035