Title :
Spin-on dielectric liner TSV for 3D wafer level packaging applications
Author :
Civale, Yann ; Majeed, Bivragh ; Tezcan, Deniz S. ; Soussan, Philippe ; Beyne, Eric
Author_Institution :
Imec, Leuven, Belgium
Abstract :
Imec is developing application specific through silicon vias (TSV) technologies for Si thicknesses of 50 and 100μm in wafer level packaging (WLP) area where thin dies are stacked and electrically connected to each other through post CMOS processed TSVs and (micro-) bumps. 3D-WLP TSV flavors are developed using spin-on dielectric polymers as isolation layer. Electrical results of the TSV-connected daisy chains and the reliability of these TSVs while undergoing thermal cycle tests is also addressed.
Keywords :
CMOS integrated circuits; elemental semiconductors; integrated circuit reliability; silicon; wafer level packaging; 3D wafer level packaging applications; Si; microbumps; post CMOS; size 100 mum; size 50 mum; spin-on dielectric liner; spin-on dielectric polymers; through silicon vias technologies; CMOS process; CMOS technology; Dielectric materials; Fabrication; Polymers; Testing; Thermal stresses; Through-silicon vias; Viscosity; Wafer scale integration;
Conference_Titel :
Interconnect Technology Conference (IITC), 2010 International
Conference_Location :
Burlingame, CA
Print_ISBN :
978-1-4244-7676-3
DOI :
10.1109/IITC.2010.5510314
