DocumentCode :
3031524
Title :
Pt vias for high temperature MEMS interconnects
Author :
Dausch, D.E. ; Gregory, C. ; Rhoades, R.L.
Author_Institution :
RTI Int., Research Triangle Park, NC, USA
fYear :
2010
fDate :
6-9 June 2010
Firstpage :
1
Lastpage :
3
Abstract :
A process sequence has been developed and characterized to fabricate interconnect structures in MEMS devices capable of withstanding thermal cycles up to at least 700°C. Via test structures with 3-7 μm diameter and 5-10 μm depth were etched in thermally oxidized silicon wafers and filled with platinum (Pt). Key enabling process steps were Pt electroplating and Pt CMP as reported herein. Target applications include piezoelectric MEMS or other devices requiring high temperature processing.
Keywords :
chemical mechanical polishing; electroplating; integrated circuit interconnections; micromechanical devices; platinum; three-dimensional integrated circuits; Pt; Pt CMP; Pt electroplating; high temperature MEMS interconnect; platinum; size 3 micron to 7 micron; size 5 micron to 10 micron; thermal cycle; thermally oxidized silicon wafer; Annealing; Electrodes; Fabrication; Metallization; Micromechanical devices; Platinum; Radio frequency; Silicon; Switches; Temperature sensors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Interconnect Technology Conference (IITC), 2010 International
Conference_Location :
Burlingame, CA
Print_ISBN :
978-1-4244-7676-3
Type :
conf
DOI :
10.1109/IITC.2010.5510316
Filename :
5510316
Link To Document :
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