Abstract :
The economic viability of the reusable core-based design paradigm depends on the development of techniques for intellectual property protection. We introduce the first dynamic watermarking technique for protecting the value of intellectual property of CAD and compilation tools and reusable core components. The essence of the new approach is the addition of a set of design and timing constraints which encodes the author´s signature. The constraints are selected in such a way that they result in minimal hardware overhead while embedding the signature which is unique and difficult to detect, remove and forge. We establish the first set of relevant metrics which forms the basis for the quantitative analysis, evaluation, and comparison of watermarking techniques. We develop a generic approach for signature data hiding in designs, which is applicable in conjunction with an arbitrary behavioral synthesis task, such as scheduling assignment, allocation, and transformations. Error correcting codes are used to augment the protection of the signature data from tampering attempts. On a large set of design examples, studies indicate the effectiveness of the new approach in a sense that the signature data, which are highly resilient, difficult to detect and remove, and yet easy to verify, can be embedded in designs with very low hardware overhead
Keywords :
circuit CAD; data encapsulation; error correction codes; high level synthesis; industrial property; timing; CAD tools; ECC; allocation; author signature encoding; behavioral synthesis techniques; compilation tools; design constraints; dynamic watermarking technique; error correcting codes; intellectual property protection; metrics; reusable core components; reusable core-based design paradigm; scheduling assignment; signature data hiding; timing constraints; transformations; Data encapsulation; Design automation; Hardware; Intellectual property; Job shop scheduling; Permission; Productivity; Protection; Timing; Watermarking;