Bandwidth, delay and energy aware optimization of global interconnects for many-core architectures

As the integrated circuit industry is moving towards many-core architectures to combat the power wall, it faces an important challenge of providing inter-core interconnects that are low power and low latency, and offer large aggregate bandwidths. This paper presents an optimal design of network-on-chip interconnects in many-core architectures. A comprehensive optimization methodology is proposed that bridges circuit and technology aspects of inter-core interconnects. The optimal global interconnect is shown to be minimum pitch and minimum dimension limited for a 1000 core chip implemented in the technology year 2015. For the same chip, it is shown that the energy per bit in global wires can be reduced by a significant margin of 16% on optimizing its width, spacing and repeater insertions. These results are drastically different from previous optimizations where the optimal width was many times larger than minimum dimension. The results presented in this paper have important implications for interconnect process development for future technology nodes and also for benchmarking emerging interconnect technologies.