Design and implementation of a scalable encryption processor with embedded variable DC/DC converter

Author

Goodman, James ; Chandrakasan, Anantha ; Dancy, Abram P.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA

fYear

1999

fDate

1999

Firstpage

855

Lastpage

860

Abstract

This work describes the design and implementation of an energy-efficient, scalable encryption processor that utilizes variable voltage supply techniques and a high-efficiency embedded variable output DC/DC converter. The resulting implementation dissipates 134 nJ/bit @ V _DD=2.5 V, when encrypting at its maximum rate of 1 Mb/s using a maximum datapath width of 512 bits. The embedded converter achieves an efficiency of 96% at this peak load. The processor is 2-3 orders of magnitude more energy efficient than optimized assembly code running on a low-power processor such as the StrongARM

Keywords

CMOS digital integrated circuits; DC-DC power convertors; cryptography; digital signal processing chips; low-power electronics; 0.6 micron; 1 Mbit/s; 134 mW; 2.5 V; 96 percent; CMOS DSP chip; embedded variable DC/DC converter; energy-efficient processor; low-power processor; scalable encryption processor; variable voltage supply techniques; Batteries; Cryptography; DC-DC power converters; Data security; Energy efficiency; Engines; Permission; Pulse width modulation converters; Throughput; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1999. Proceedings. 36th

Conference_Location

New Orleans, LA

Print_ISBN

1-58113-092-9

Type

conf

DOI

10.1109/DAC.1999.782164

Filename

782164