Title :
Circuit complexity reduction for symbolic analysis of analog integrated circuits
Author :
Daems, Walter ; Gielen, Georges ; Sansen, Willy
Author_Institution :
ESAT, Katholieke Univ., Leuven, Heverlee, Belgium
Abstract :
This paper presents a method to reduce the complexity of a linear or linearized (small-signal) analog circuit. The reduction technique, based on quality-error ranking, can be used as a standard reduction engine that ensures the validity of the resulting network model in a specific (set of) design point(s) within a given frequency range and a given magnitude and phase error. It can also be used as an analysis engine to extract symbolic expressions for poles and zeroes. The reduction technique is driven by analysis of the signal flow graph associated with the network model. Experimental results show the effectiveness of the approach
Keywords :
analogue integrated circuits; circuit analysis computing; circuit complexity; integrated circuit modelling; poles and zeros; signal flow graphs; symbol manipulation; SFG analysis; analog IC design; analog integrated circuits; analysis engine; circuit complexity reduction; network model; poles and zeroes; quality-error ranking; signal flow graph; small-signal analog circuit; standard reduction engine; symbolic analysis; Analog circuits; Analog integrated circuits; Circuit analysis; Complexity theory; Electronic circuits; Engines; Frequency; Performance analysis; Permission; Vectors;
Conference_Titel :
Design Automation Conference, 1999. Proceedings. 36th
Conference_Location :
New Orleans, LA
Print_ISBN :
1-58113-092-9
DOI :
10.1109/DAC.1999.782235
