A reduced area scheme for carry-select adders

For a medium-speed addition application, a carry-skip adder is usually preferred over a carry-select adder, due to its smaller area. A reduced-area carry-select adder scheme in which the second copy of the carry-chain is substituted by an OR gate per bit position is proposed. This alternative implementation for a carry-select adder reduces the relative area advantage of a carry-skip adder to roughly 35%. Replacing the ripple-carry blocks with parallel-prefix blocks results in a select-prefix adder with a slightly better area and time than a parallel-prefix adder