Title :
Boolean technology mapping for both ECI and CMOS circuits based on permissible functions and binary decision diagrams
Author :
Sato, Hitomi ; Takahashi, Noboru ; Matsunaga, Yusuke ; Fujita, Masahiro
Author_Institution :
Fujitsu Ltd., Tokyo, Japan
Abstract :
A Boolean technology mapping with permissible functions is presented. This technique makes use of complementary intermediate logic functions of circuits. Therefore, complementary outputs of ECL gates can be easily handled. High-quality synthesized ECL circuits and CMOS circuits free of logical redundancies are generated. Technology-independent networks are converted into technology-dependent virtual gates network. Virtual gates have an arbitrary number of fan-ins. CMOS virtual networks consist of only NOR and NAND gates, while ECL virtual networks consist of only OR gates (but each gate has complementary outputs). By considering logic function and the device restrictions these virtual gate networks are translated into cell networks using permissible functions
Keywords :
Boolean functions; CMOS integrated circuits; emitter-coupled logic; integrated logic circuits; logic design; logic testing; Boolean technology mapping; CMOS circuits; ECI; NAND; NOR; binary decision diagrams; complementary intermediate logic functions; permissible functions; technology-dependent virtual gates network; Boolean functions; CMOS logic circuits; CMOS technology; Circuit synthesis; Circuit topology; Data structures; Integrated circuit technology; Libraries; Logic functions; Network synthesis;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2079-X
DOI :
10.1109/ICCD.1990.130228
