Title :
BiCMOS fault models: is stuck-at adequate?
Author :
Levitt, Marc E. ; Roy, Kaushik ; Abraham, Jacob A.
Author_Institution :
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Abstract :
The adequacy of the stuck-at fault model for BiCMOS logic is investigated. Realistic failures in basic logic blocks are examined, and their coverage by the stuck-at model is explored. It is shown that the static stuck-at model cannot cover the complete range of possible failures, and more importantly, tests for stuck-at faults will not detect realistic features in BiCMOS technology. This is because most open faults manifest themselves as delay failures. Through the use of transient analysis it is shown that the only way to insure proper functioning of BiCMOS circuits is to test for delay faults
Keywords :
BIMOS integrated circuits; integrated circuit testing; integrated logic circuits; logic testing; transients; BiCMOS fault models; BiCMOS logic; delay failures; stuck-at fault model; transient analysis; BiCMOS integrated circuits; CMOS technology; Circuit faults; Circuit simulation; Circuit testing; Delay; Performance analysis; Performance evaluation; Semiconductor device modeling; Transient analysis;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2079-X
DOI :
10.1109/ICCD.1990.130231
