Influence of gate geometry in integrated MOS varactors on accumulation mode for RF

Author

Amselem, E. ; González, B. ; García, J. ; Aldea, I. ; Marrero, M. ; Iturri, A.G. ; Pino, J. Del ; Khemchandani, S.L. ; Hernández, A.

Author_Institution

Univ. de Las Palmas de Gran Canaria, Las Palmas

fYear

2007

fDate

Jan. 31 2007-Feb. 2 2007

Firstpage

68

Lastpage

71

Abstract

Driven by the many applications that varactors have in RF integrated blocks, this work analyzes the influence of gate geometry (width and length) on integrated accumulation MOS varactors. For this purpose, a number of varactors have been designed and fabricated on a 0.8 mum CMOS standard technology. The most relevant parameters: quality factor, tuning range, and capacitance, are simulated and compared against measurements. Some design considerations are reported.

Keywords

CMOS integrated circuits; MOS integrated circuits; radiofrequency integrated circuits; varactors; CMOS; RF integrated blocks; gate geometry; integrated accumulation MOS varactors; quality factor; size 0.8 mum; tuning range; CMOS technology; Capacitance measurement; Circuit simulation; Fabrication; Geometry; Integrated circuit measurements; Q factor; Radio frequency; Varactors; Voltage; MOS; RF; integrated circuit; varactor;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices, 2007 Spanish Conference on

Conference_Location

Madrid

Print_ISBN

1-4244-0868-7

Type

conf

DOI

10.1109/SCED.2007.383997

Filename

4271170