Title :
A 75 MHz CMOS digital convolver
Author :
Rose, P.J. ; Koether, B.G.
Author_Institution :
Boeing Aerosp. & Electron., Seattle, WA, USA
Abstract :
A dynamic logic digital convolver utilizing a 1-μm commercial CMOS process has been developed. The convolver is a linear systolic array with a time-bandwidth product of 1024 and a processing gain of nearly 30 dB. It features a single-phase clock with dynamic D flip-flops as the basic storage elements. The device, in a four-chip set, acts as a matched filter which is intended to compare a noise-like signal against a reference signal. The input buffers incorporate ESD protection diodes and convert TTL to CMOS levels. The output buffers use transistors sized to drive 20-pF loads with CMOS levels (TTL-compatible) signals with rise and fall times of less than 1 ns. Design and performance of the convolver are determined
Keywords :
CMOS integrated circuits; digital signal processing chips; systolic arrays; 1 micron; 30 dB; 75 MHz; 75 MHz CMOS digital convolver; CMOS process; ESD protection diodes; TTL; TTL-compatible; dynamic D flip-flops; dynamic logic digital convolver; linear systolic array; matched filter; noise-like signal; reference signal; single-phase clock; CMOS logic circuits; CMOS process; Clocks; Convolvers; Electrostatic discharge; Flip-flops; Logic devices; Matched filters; Protection; Systolic arrays;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2079-X
DOI :
10.1109/ICCD.1990.130236
