Circuit-level modeling of spot defects

Author

Gaitonde, Dinesh ; Walker, D.M.H.

Author_Institution

Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

fYear

1991

fDate

18-20 Nov 1991

Firstpage

63

Lastpage

66

Abstract

Describes some of the problems faced in mapping spot defects (e.g. extra/missing material, gate oxide pinholes) to changes in the nominal circuit. Traditionally, a very simple mapping has been used, with circuit faults assumed to consist of shorts, opens and occasionally, extra devices. The authors discuss some of the problems in achieving the simple mapping and how they are solved in VLASIC catastrophic fault yield simulator. They also describe modeling problems that appear to require full 3-D device simulation. Finally some investigations into the hazy boundary between parametric and functional faults are described

Keywords

MOS integrated circuits; circuit analysis computing; semiconductor device models; 3-D device simulation; VLASIC catastrophic fault yield simulator; circuit faults; circuit level modeling; functional faults; gate oxide pinholes; modeling problems; parametric faults; spot defects mapping; Circuit faults; Circuit simulation; Circuit testing; Circuit topology; Conferences; Data mining; Fault tolerant systems; Statistics; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance on VLSI Systems, 1991. Proceedings., 1991 International Workshop on

Conference_Location

Hidden Valley, PA

ISSN

1550-5774

Print_ISBN

0-8186-2457-4

Type

conf

DOI

10.1109/DFTVS.1991.199946

Filename

199946