Title :
Knowledge-based electrical monitor approach using very large array yield structures to delineate defects during process development and production yield improvement
Author :
Hammond, Jim ; Sery, George
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
A knowledge-based system has been developed for a set of very large electrical test pattern structures that allows one to understand and debug process problems in sub-micron EPROM/Flash technology. These structures are called `MONGOS´ due to their size (~300 K Cells) and were designed using the process target EPROM or Flash cells in an array as an exact replica of the product vehicle. Resistance and IV measurements, on pieces of the MONGOs complete with gate and substrate bias control, provide raw data input. The entire 300 K cells can be treated like one giant transistor. A post-processor program creates defect bins from these data for each layer deconfounding the defects according to rules defined in a set of calculation files. The approach is flexible in that defect bins (models) can be defined and implemented as mechanisms are refined; it is also fast since >300 K cells are tested in parallel. Thus, process improvements can be engineered much faster
Keywords :
EPROM; MOS integrated circuits; VLSI; integrated memory circuits; knowledge based systems; EPROM; Flash cells; IV measurements; MONGOS; VLSI; defect bins; delineate defects; knowledge based electrical monitor; knowledge-based system; parallel testing; post-processor program; process development; production yield improvement; substrate bias control; very large array yield structures; very large electrical test pattern structures; EPROM; Knowledge based systems; Logic arrays; Logic testing; Monitoring; Process design; Production; Reverse engineering; System testing; Vehicles;
Conference_Titel :
Defect and Fault Tolerance on VLSI Systems, 1991. Proceedings., 1991 International Workshop on
Conference_Location :
Hidden Valley, PA
Print_ISBN :
0-8186-2457-4
DOI :
10.1109/DFTVS.1991.199947