A model for enhanced manufacturability of defect tolerant integrated circuits

Author

Koren, Zahava ; Koren, Israel

Author_Institution

Massachusetts Univ., Amherst, MA, USA

fYear

1991

fDate

18-20 Nov 1991

Firstpage

81

Lastpage

92

Abstract

Many factors contribute the the cost of manufacturing integrated circuits. These include the yield of the design IC, the complexity of its testing, the packaging cost, etc. and they all must be taken into account when designing a defect tolerant integrated circuit. The authors present a mathematical model which includes all major factors contributing to the cost of manufacturing ICs. This model allows the determination of the design which maximizes the expected profit rather than maximizing the yield. Numerical examples illustrating the proposed model are also presented

Keywords

VLSI; integrated circuit manufacture; optimisation; redundancy; IC manufacture costs; defect tolerant integrated circuits; major factors; manufacturability; mathematical model; model; packaging cost; profit maximisation; yield; Circuit faults; Computer aided manufacturing; Computer integrated manufacturing; Cost function; Integrated circuit manufacture; Integrated circuit modeling; Packaging; Pulp manufacturing; Testing; Virtual manufacturing;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance on VLSI Systems, 1991. Proceedings., 1991 International Workshop on

Conference_Location

Hidden Valley, PA

ISSN

1550-5774

Print_ISBN

0-8186-2457-4

Type

conf

DOI

10.1109/DFTVS.1991.199948

Filename

199948