Neural networks on silicon: the mapping of hardware faults onto behavioral errors

The problem of defect- and fault-tolerance in neural networks becomes increasingly important as a growing number of silicon implementations become available and mission-critical applications are envisioned. As an alternative to architecture-specific policies, intrinsic characteristics of the neural paradigm with respect to a functional error model are considered. In particular, this has been done for multilayered back-propagation networks, where both the classification errors induced by insurgence of a fault and the possibility of masking such errors through a repeated learning phase have been studied. Such abstract results can be used to analyze various silicon architectures implementing the multi-layered nets; physical faults are mapped onto the functional error classes, so as the evaluate both the intrinsic robustness of the various architectures and their critical areas, where ad-hoc design modifications or redundancies must be inserted to increase fault-tolerance properties. In the present paper some relevant implementations, representative of various design philosophies, are considered from this point of view