Title :
Effects of fault tolerance on the reliability of memory array supports
Author :
Aichelmann, F.J., Jr.
Author_Institution :
IBM Gen. Technol. Div., Hopewell Junction, NY, USA
Abstract :
For future-generation large-scale computers, memory reliability is independent of the memory chip failures due to low failure rates and fault-tolerant techniques. When failures do occur, they are masked, using such techniques as single error correction (SEC), page deallocation, and array chip sparing. The two remaining sources of failures are card(s) and logic support modules. This paper describes a method to minimize the effects of logic fails by using logic redundancy
Keywords :
fault tolerant computing; reliability; semiconductor storage; array chip sparing; cards; fault tolerance; fault-tolerant techniques; large-scale computers; logic redundancy; logic support modules; memory array supports; memory chip failures; memory reliability; page deallocation; reliability; single error correction; Circuits; Costs; Error correction; Fault tolerance; Large-scale systems; Logic arrays; Logic design; Redundancy; Semiconductor memory;
Conference_Titel :
Defect and Fault Tolerance on VLSI Systems, 1991. Proceedings., 1991 International Workshop on
Conference_Location :
Hidden Valley, PA
Print_ISBN :
0-8186-2457-4
DOI :
10.1109/DFTVS.1991.199954
