Title :
Concurrent error diagnosis in mesh array architectures based on overlapping H-processes
Author :
Manolakos, E.S. ; Dakhil, D. ; Vai, M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
Abstract :
Unlike other methods for concurrent error detection and location (CED), the one proposed is not application specific and does not require fault free comparators and custom VLSI design for the processing cells. It is suitable for any algorithm that can be decomposed in block operations of the format [(a op1 b) op2 (c op3 d)], where a, b, c, d are arbitrary operands and op1 , op2, op3 dyadic operators. The process of computing such an operation in a distributed and redundant way on an H-tree shaped sub-array is called an H-process. Many H-processes can overlap providing a general purpose mechanism for run-time fault tolerance in data driven mesh array architectures. Errors can be detected during normal operation. Suspected erroneous results can be masked while location is attempted. There is no need for retries. Diagnosis is achieved `on the fly´ without graceful degradation, upon detection
Keywords :
fault tolerant computing; parallel architectures; H-tree shaped sub-array; concurrent error detection; general purpose mechanism; general purpose scheme; mesh array architectures; on the fly diagnosis; overlapping H-processes; run-time fault tolerance; Computer architecture; Computer errors; Concurrent computing; Delay; Design engineering; Fault tolerance; Hardware; Redundancy; Signal processing algorithms; Very large scale integration;
Conference_Titel :
Defect and Fault Tolerance on VLSI Systems, 1991. Proceedings., 1991 International Workshop on
Conference_Location :
Hidden Valley, PA
Print_ISBN :
0-8186-2457-4
DOI :
10.1109/DFTVS.1991.199955