A new approach to modeling the performance of a class of fault tolerant VLSI/WSI systems based on multiple-level redundancy

Author

Chen, Yung-Yuan ; Upadhyaya, Shambhu J.

Author_Institution

Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA

fYear

1991

fDate

18-20 Nov 1991

Firstpage

157

Lastpage

160

Abstract

The on-chip redundancy left unused in a fault tolerant system after successfully reconfiguring and eliminating the manufacturing defects is called residual redundancy. This redundancy can be used to improve the operational reliability of the system. The authors present a new hierarchical model to analyze the effect of residual redundancy on performance improvement of a class of fault tolerant VLSI/WSI systems based on multiple-level redundancy. Their model emphasizes the effect of support circuit (interconnection) failures on system reliability, a practical issue of great concern in WSI technology. Results of a simulation conducted to validate their model are discussed

Keywords

VLSI; fault tolerant computing; modelling; parallel architectures; redundancy; reliability; VLSI; WSI; fault tolerant system; hierarchical model; interconnection failures effect; modeling; multiple-level redundancy; on-chip redundancy; operational reliability; performance improvement; residual redundancy; system reliability; Circuit faults; Circuit simulation; Fault tolerant systems; Integrated circuit interconnections; Manufacturing; Performance analysis; Redundancy; Reliability; System-on-a-chip; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance on VLSI Systems, 1991. Proceedings., 1991 International Workshop on

Conference_Location

Hidden Valley, PA

ISSN

1550-5774

Print_ISBN

0-8186-2457-4

Type

conf

DOI

10.1109/DFTVS.1991.199957

Filename

199957