Title :
A bottom-up methodology to characterize delay faults
Author :
Zubairi, Junaid ; Craig, Gary L.
Author_Institution :
Syracuse Univ., NY, USA
Abstract :
Inductive Fault Analysis is extended to consider localized spot defects in CMOS VLSI circuits which impact circuit timing performance. A scheme of deterministic introduction of spot defects into layouts of combinational logic circuits is described. A methodology and tool is developed to characterize delay defects resulting from missing and extra spot defects and to generate realistic delay defect distribution
Keywords :
CMOS integrated circuits; VLSI; combinatorial circuits; integrated circuit testing; logic testing; CMOS VLSI; bottom-up methodology; circuit timing performance; combinational logic circuits; defect injection; delay faults characterisation; inductive fault analysis; spot defects; Circuit faults; Circuit simulation; Circuit testing; Delay; Logic design; Logic testing; Manufacturing; Performance analysis; Timing; Very large scale integration;
Conference_Titel :
Defect and Fault Tolerance on VLSI Systems, 1991. Proceedings., 1991 International Workshop on
Conference_Location :
Hidden Valley, PA
Print_ISBN :
0-8186-2457-4
DOI :
10.1109/DFTVS.1991.199961
