Title :
Delay fault simulation of self-checking error checkers
Author :
Hirabayashi, Kanji
Author_Institution :
ULSI Res. Center, Toshiba Corp., Kawasaki, Japan
Abstract :
A robustly-tested gate-delay fault model is proposed using 7-valued logic, and applied to the delay fault simulation of self-checking error checkers. The simulated results are compared with those obtained using either a nonrobustly-tested gate-delay fault model or a path-delay fault model. Experiments show that the robustly-tested gate-delay fault model gives the most pessimistic evaluation for delay test effectiveness. The CMOS pass transistor logic implementation of the self-checking error checkers is discussed
Keywords :
CMOS integrated circuits; VLSI; integrated circuit testing; logic testing; many-valued logics; CMOS pass transistor logic; delay fault simulation; gate-delay fault model; pessimistic evaluation; robustly tested model; self-checking error checkers; simulated results; Automatic testing; CMOS logic circuits; Circuit faults; Circuit testing; Delay; Fault detection; Logic testing; Rails; Robustness; Semiconductor device modeling;
Conference_Titel :
Defect and Fault Tolerance on VLSI Systems, 1991. Proceedings., 1991 International Workshop on
Conference_Location :
Hidden Valley, PA
Print_ISBN :
0-8186-2457-4
DOI :
10.1109/DFTVS.1991.199962
