Title :
Parallel Genetic Algorithm for VLSI Standard Cell Placement
Author :
Subbaraj, P. ; Sankar, Saravana S. ; Anand, S.
Author_Institution :
Kalasalingam Univ., Krishnankoil, India
Abstract :
This work addresses the methods to solve VLSI standard cell placement problem with the objectives of minimizing the wire length and computational time. In this work a parallel GA architecture is designed and the computational time of Genetic algorithm is reduced by means of parallel technique. The proposed algorithms are tested in IBM bench mark circuits. Proposed method is compared with Qplace5.1.67,, Dragon 2.2.3 and Fastplace are found superior in terms of computational time and solution quality.
Keywords :
VLSI; genetic algorithms; integrated circuit layout; minimisation; VLSI standard cell placement; computational time minimization; parallel genetic algorithm architecture; wire length minimization; Algorithm design and analysis; Circuit simulation; Circuit testing; Concurrent computing; Genetic algorithms; Integrated circuit interconnections; Simulated annealing; Telecommunication computing; Very large scale integration; Wire; Genetic Algorithm; VLSI physical design; parallel computing; placement;
Conference_Titel :
Advances in Computing, Control, & Telecommunication Technologies, 2009. ACT '09. International Conference on
Conference_Location :
Trivandrum, Kerala
Print_ISBN :
978-1-4244-5321-4
Electronic_ISBN :
978-0-7695-3915-7
DOI :
10.1109/ACT.2009.30
