A 90-nm radiation hardened clock spine

A RHBD clock distribution network is described that reliably synchronizes the flow of signals through an integrated circuit in the presence of SETs. The clock spine design controls both redundant and non-redundant hardened circuits. The design uses techniques to reduce the jitter due to SETs, as well as error detection at every clock edge, since errors may be in the clock gating enables rather than the clocks themselves. The clock spine has been fabricated and tested on both standard and a low power 90-nm test chips, and proven hard as demonstrated by both heavy ion and proton broad beam testing.