• DocumentCode
    3033379
  • Title

    A hierarchical floorplanning approach

  • Author

    Pedram, Massoud ; Preas, Bryan

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
  • fYear
    1990
  • fDate
    17-19 Sep 1990
  • Firstpage
    332
  • Lastpage
    338
  • Abstract
    A hierarchical floorplanner for general cell layout that exploits accurate shape functions that describe constraints on the leaf cells in order to produce good floorplans is presented. The leaf cells may have highly constrained shapes, or more flexible shapes. The floorplanner trades off the locations, sizes shapes, and pin positions of the cell against each other in order to minimize the layout area and the amount of interconnections. To the extent that the shape functions are accurate, there is no need for design iterations. By imposing a hierarchy in the form of a multiwave cluster tree, the number of floorplanning options is restricted and the problem is simplified by allowing the floorplanner to operate on one hierarchical cell at a time. The shape functions and the hierarchical approach make it possible to directly compute locations, sizes, shapes, and pin positions for the leaf cells
  • Keywords
    VLSI; circuit layout CAD; constraints; flexible shapes; general cell layout; hierarchical cell; hierarchical floorplanning; interconnections; layout area; leaf cells; locations; multiwave cluster tree; pin positions; shape functions; sizes; Computer science; Laboratories; Logic arrays; Predictive models; Process control; Process design; Programmable logic arrays; Read only memory; Shape control; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on
  • Conference_Location
    Cambridge, MA
  • Print_ISBN
    0-8186-2079-X
  • Type

    conf

  • DOI
    10.1109/ICCD.1990.130243
  • Filename
    130243