Title :
A 6.93-/spl mu/m/sup 2/ n-gate full CMOS SRAM cell technology with high-performance 1.8-V dual-gate CMOS for peripheral circuits
Author :
Minami, M. ; Ohki, N. ; Ishida, H. ; Yamanaka, T. ; Ishibashi, K. ; Shimizu, A. ; Kure, T. ; Nishida, T. ; Nagano, T.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
A high-performance microprocessor-compatible small size full CMOS SRAM cell technology has been developed. A 0.3-/spl mu/m gate length load pMOSFET, formed utilizing amorphous-Si-film through-channel implantation, is merged with a 0.25-/spl mu/m gate length pMOSFET for the peripheral circuits. Mask-free contact for TiN local interconnect is developed with wet etching. A 6.93-/spl mu/m/sup 2/ cell area and a high-performance 1.8-V circuit are thus realized.
Keywords :
CMOS memory circuits; SRAM chips; integrated circuit technology; ion implantation; 0.25 micron; 0.3 micron; 1.8 V; Si; TiN; TiN local interconnect; amorphous-Si-film through-channel implantation; dual-gate CMOS; load pMOSFET; n-gate full CMOS SRAM cell technology; peripheral circuits; wet etching; CMOS technology; Circuit optimization; Integrated circuit interconnections; Laboratories; MOSFET circuits; Random access memory; Tin; Ultra large scale integration; Voltage; Wet etching;
Conference_Titel :
VLSI Technology, 1995. Digest of Technical Papers. 1995 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
0-7803-2602-4
DOI :
10.1109/VLSIT.1995.520836
