Title :
Worst-case test vectors of sequential ASiCS exposed to total dose
Author :
Abou-Auf, A.A. ; Abdel-Aziz, M.M. ; Abdel-Aziz, H.A. ; Wassal, A.G.
Author_Institution :
Electron. Eng. Dept., American Univ. in Cairo, AUC, New Cairo, Egypt
Abstract :
We introduce a novel methodology for identifying worst-case test vectors for sequential circuits in ASIC devices exposed to total dose. Testing of sequential circuits requires the use of sequence of test vectors. Those test vectors we generated using cell-level fault models for failures induced by total dose. In this paper we focused on three types of failures: logic, leakage current, and delay failures. A novel cell-level fault model for delay failures induced by total dose is introduced in this paper. This methodology was validated using SPICE simulation as well as experimental results.
Keywords :
application specific integrated circuits; fault diagnosis; integrated circuit testing; logic testing; radiation effects; sequential circuits; ASIC devices; SPICE simulation; cell-level fault models; delay failure; leakage current failure; logic failure; sequential circuit testing; worst-case test vectors; Circuit faults; Combinational circuits; Delay; Integrated circuit modeling; Radiation effects; Sequential circuits; Vectors;
Conference_Titel :
Radiation and Its Effects on Components and Systems (RADECS), 2011 12th European Conference on
Conference_Location :
Sevilla
Print_ISBN :
978-1-4577-0585-4
DOI :
10.1109/RADECS.2011.6131393
