Cycle-accurate configuration layer model for Xilinx Virtex FPGAs

Author

Herrera-Alzu, I. ; López-Vallejo, M.

Author_Institution

Dept. of Electron. Eng., Univ. Politec. de Madrid, Madrid, Spain

fYear

2011

fDate

19-23 Sept. 2011

Firstpage

182

Lastpage

185

Abstract

A cycle-accurate VHDL simulation model for the Xilinx Virtex-4 (and on) FPGA Configuration Layer is presented. This model allows for simulating configuration memory SEU injection and correction dynamics, as well as control logic SEFI recovery, with independence from Application Layer. Scrubber designs can be efficiently simulated, together with one or more instances of this model, prior to hardware implementation. This significantly improves design observability and simplifies the validation of such designs.

Keywords

digital simulation; field programmable gate arrays; hardware description languages; integrated circuit modelling; radiation hardening (electronics); Xilinx Virtex FPGA configuration layer; configuration memory SEU correction dynamics; configuration memory SEU injection; control logic SEFI recovery; cycle-accurate VHDL simulation model; cycle-accurate configuration layer model; scrubber designs; Analytical models; Computational modeling; Fault tolerant systems; Field programmable gate arrays; Hardware; Random access memory; Single event upset; Configuration layer; FPGA; SEFI; SEU; fault injection; radiation effects; scrubber; simulation model;

fLanguage

English

Publisher

ieee

Conference_Titel

Radiation and Its Effects on Components and Systems (RADECS), 2011 12th European Conference on

Conference_Location

Sevilla

ISSN

0379-6566

Print_ISBN

978-1-4577-0585-4

Type

conf

DOI

10.1109/RADECS.2011.6131394

Filename

6131394