Copper integration into 0.5 /spl mu/m BiCMOS technology

Author

Gelatos, A.V. ; Nguyen, B.-Y. ; Perry, K. ; Marsh, R. ; Peschke, J. ; Filipiak, S. ; Travis, E. ; Bhat, N. ; La, L.B. ; Thompson, M. ; Saaranen, T. ; Tobin, P.J.

Author_Institution

Motorola Inc., Austin, TX, USA

fYear

1995

fDate

6-8 June 1995

Firstpage

25

Lastpage

26

Abstract

The report describes the integration of copper into the backend of a two-level metal 0.5 /spl mu/m BiCMOS SRAM circuit. The circuit is used to evaluate the impact of copper on the device characteristics. The results of time dependent gate dielectric breakdown, gate oxide interface state generation, temperature dependent reverse diode leakage, and hot carrier injection are used to demonstrate that, under standard backend processing conditions, copper does not degrade device performance.

Keywords

BiCMOS memory circuits; SRAM chips; electric breakdown; hot carriers; integrated circuit metallisation; interface states; leakage currents; 0.5 micron; BiCMOS technology; Cu; backend processing conditions; device characteristics; gate oxide interface state generation; hot carrier injection; submicron process; temperature dependent reverse diode leakage; time dependent gate dielectric breakdown; two-level metal SRAM circuit; BiCMOS integrated circuits; Circuit testing; Copper; Human computer interaction; Interface states; Paper technology; Silicon; Stress; Temperature dependence; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1995. Digest of Technical Papers. 1995 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

0-7803-2602-4

Type

conf

DOI

10.1109/VLSIT.1995.520842

Filename

520842