Title :
Fully integrated multilevel interconnect process for low cost sub-half-micron ASIC applications
Author :
Norishima, M. ; Matsuno, T. ; Anand, M.B. ; Murota, M. ; Inohara, M. ; Inoue, K. ; Ohtani, H. ; Miyamoto, K. ; Ogawa, R. ; Seto, M. ; Fukuhara, C. ; Shibata, H. ; Kakumu, M.
Author_Institution :
Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan
Abstract :
Back-end-of-the line (BEOL) interconnect process integration for sub-half-micron ASIC applications with both low-cost merit and appropriately high performance is presented. Borderless and stacked contact/via structures to reduce chip size and minimization of ILD thickness without performance degradation are achieved. Blind-CMP, selective tungsten CVD, and fluorine-TEOS ILD with low dielectric constant are selected with process simplification in mind.
Keywords :
application specific integrated circuits; integrated circuit interconnections; 0.5 micron; W; back-end-of-the line; blind-CMP; borderless contact/via structures; chip size; dielectric constant; fluorine-TEOS ILD thickness; low cost sub-half-micron ASIC; multilevel interconnect; process integration; selective tungsten CVD; stacked contact/via structures; Aluminum; Application specific integrated circuits; Costs; Degradation; Dielectric constant; Etching; Integrated circuit interconnections; Plugs; Silicides; Tungsten;
Conference_Titel :
VLSI Technology, 1995. Digest of Technical Papers. 1995 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
0-7803-2602-4
DOI :
10.1109/VLSIT.1995.520853
