Title :
High performance 0.3 /spl mu/m CMOS using I-line lithography and BARC
Author :
Thakar, G.V. ; Madan, S.K. ; Garza, C.M. ; Krisa, W.L. ; Nicollian, P.E. ; Wise, J.L. ; Lee, C.K. ; McKee, J.A. ; Appel, A.T. ; Esquivel, A.L. ; McNeil, V.M. ; Prinslow, D.A. ; Riemenschneider, B.R. ; Utsumi, T. ; Eklund, R.H. ; Chapman, R.A.
Author_Institution :
Semicond. Process & Design Center, Texas Instrum. Inc., Dallas, TX, USA
Abstract :
TiN or organic Bottom AntiReflection Coatings (BARC), polysilicon hammerheads, phase shift masks, quadrupole off-axis illumination I-line lithography at N.A.=0.60, shallow source/drain extenders, LOCOS isolation, and 6 nm gate oxide are used to obtain high performance 0.30 /spl mu/m 2.5 V CMOS with effective channel lengths <0.20 /spl mu/m. The use of BARC reduces off current and improves PMOS hot carrier reliability.
Keywords :
CMOS integrated circuits; VLSI; antireflection coatings; hot carriers; integrated circuit reliability; integrated circuit technology; isolation technology; phase shifting masks; photolithography; 0.3 micron; 2.5 V; 6 nm; BARC; CMOS; I-line lithography; LOCOS isolation; TiN; VLSI; bottom antireflection coatings; effective channel lengths; gate oxide; hot carrier reliability; off current; phase shift masks; polysilicon hammerheads; quadrupole off-axis illumination; shallow source/drain extenders; Annealing; Boron; Coatings; Degradation; Etching; Hot carriers; Instruments; Lithography; Surfaces; Tin;
Conference_Titel :
VLSI Technology, 1995. Digest of Technical Papers. 1995 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
0-7803-2602-4
DOI :
10.1109/VLSIT.1995.520865
