DocumentCode :
3034415
Title :
Novel test circuit structures using selectively metal-covered transistors for a laser irradiation upset analysis
Author :
Hatano, Hiroshi
Author_Institution :
Dept. of Electr. & Electron. Eng., Shizuoka Inst. of Sci. & Technol., Fukuroi, Japan
fYear :
2011
fDate :
19-23 Sept. 2011
Firstpage :
458
Lastpage :
462
Abstract :
A quick and easy laser experiment for photocurrent induced upset investigations has been described as a preliminary test method for SEE experiments. In order to focus a laser beam on a desired transistor in complex LSI circuits, novel test circuit structures using selectively metal-covered transistors have been proposed. Photocurrent induced upsets have been successfully observed in a target CMOS inverter with an SR-FF detector. The laser irradiation upset has also been successfully observed in a selectively metal-covered CMOS SRAM cell. SEE test results are not explicitly shown in this paper.
Keywords :
CMOS memory circuits; MOSFET; integrated circuit testing; invertors; large scale integration; radiation hardening (electronics); CMOS inverter; SEE; SR-FF detector; complex LSI circuits; laser beam; laser experiment; laser irradiation upset analysis; metal-covered CMOS SRAM cell; metal-covered transistors; photocurrent induced upset investigations; preliminary test method; test circuit structures; CMOS integrated circuits; Detectors; Inverters; Lasers; Radiation effects; Random access memory; Transistors; Circuit analysis; design methodology; metal-covered transistor; photocurrent induced failure;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Radiation and Its Effects on Components and Systems (RADECS), 2011 12th European Conference on
Conference_Location :
Sevilla
ISSN :
0379-6566
Print_ISBN :
978-1-4577-0585-4
Type :
conf
DOI :
10.1109/RADECS.2011.6131422
Filename :
6131422
Link To Document :
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