Title :
A 64-bit floating-point processing unit with a horizontal instruction code for parallel operations
Author :
Katsuno, Akira ; Takahashi, Hiromasa ; Kubosawa, Hajime ; Sato, Tomio ; Suga, Atsuhiro ; Goto, Gensuke
Author_Institution :
Fujitsu Lab. Ltd., Kanagawa, Japan
Abstract :
A full 64-bit floating-point processing unit (FPU) with a long horizontal instruction code for parallel operations without pipeline interlock is described. The FPU is implemented on a 1.0-μm CMOS chip containing 300 K transistors and operating at 25 MHz. It runs at a peak rate of 50 MFLOPs and a sustained rate of 15.4 MFLOPs. The register-to-register latency of double and single-precision addition, subtraction and multiplication are 120 ns each. The latency of double-precision division is 640 ns and that of square root is 880 ns
Keywords :
CMOS integrated circuits; digital arithmetic; microprocessor chips; 1.0 micron; 1.0-μm CMOS chip; 120 ns; 15.4 MFLOPS; 25 MHz; 50 MFLOPS; 50 MFLOPs; 64 bit; 64-bit floating-point processing unit; 640 ns; 880 ns; double-precision division; horizontal instruction code; parallel operations; register-to-register latency; square root; Computer aided instruction; Computer architecture; Delay; Floating-point arithmetic; Hardware; High performance computing; Laboratories; Pipelines; Reduced instruction set computing; System buses;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2079-X
DOI :
10.1109/ICCD.1990.130250
