Title :
A low power current sensing scheme for cmos sram
Author :
Wang, H. ; Liu, P.C.
Author_Institution :
Nanyang Technological University
Keywords :
Circuit simulation; Clocks; Energy consumption; Inverters; Latches; Parasitic capacitance; Random access memory; Signal design; Timing; Voltage;
Conference_Titel :
Memory Technology, Design and Testing, 1996. Records of the 1996 IEEE International Workshop on
Print_ISBN :
0-8186-7466-0
DOI :
10.1109/MTDT.1996.782489
