A 0.3GHz–3.3GHz highly linear CMOS LNA for multimode applications

The proposed low noise amplifier was implemented in IBM 0.13um CMOS technology. Powered by a 1.2 V supply and the simulated DC current consumption is only 10.9mA. In Figure 7, S11 is below -10dB ranging from 300MHz to 3.3GHZ, with a bandwidth of around 3GHz. S21indicates the gain of the LNA. As shown, the gain of higher than 10dB is over the frequency 400MHz to 6GHz. The Noise Figure (NF) is plotted in Figure 8. NFs of the LNA are all below 2dB in the frequency ranging from 300MHz to 5.6GHz. The IIP3 of the LNA was examined at seven different frequencies with 200 MHz frequency spacing at -20 dBm. As shown in Figure 9, an IIP3 improvement greater than 6.2 dB is achieved in worst case. Simulation results prove that the proposed linearization technique is effective for wideband LNA. The circuit performances are summarized in Table I and compared with other designed wideband LNAs. The proposed design achieves the lowest NF and highest IIP3 in a wide bandwidth with a moderate power consumption.