Title :
PRAM cell technology and characterization in 20nm node size
Author :
Kang, M.J. ; Park, T.J. ; Kwon, Y.W. ; Ahn, D.H. ; Kang, Y.S. ; Jeong, H. ; Ahn, S.J. ; Song, Y.J. ; Kim, B.C. ; Nam, S.W. ; Kang, H.K. ; Jeong, G.T. ; Chung, C.H.
Author_Institution :
New Memory Lab., Samsung Electron. Co. Ltd., Hwasung, South Korea
Abstract :
We reported characteristics of 20nm PRAM cell. Optimization of diode integration process and improved implantation technology were used to satisfy the required diode on-current (Ion) with low off-current (Ioff). Confined cell structure and novel bottom electrode (BE) materials were developed to reduce a reset current (Ireset) below 100uA. Using the advanced technologies, we successfully produced fully integrated 20nm node size PRAM device for the first time.
Keywords :
electrodes; optimisation; random-access storage; semiconductor diodes; PRAM cell technology; bottom electrode materials; confined cell structure; diode integration process optimization; diode off-current; diode on-current; implantation technology; reset current reduction; size 20 nm; Computer architecture; Heating; Microprocessors; Phase change random access memory; Resistance; Schottky diodes;
Conference_Titel :
Electron Devices Meeting (IEDM), 2011 IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4577-0506-9
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2011.6131478
