DocumentCode :
3035860
Title :
Performance evaluation of modified hierarchical ring by exploiting link utilization and memory access locality
Author :
Kwak, Jong Wook ; Jho, Chu Shik
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ.
fYear :
2005
fDate :
21-21 Dec. 2005
Firstpage :
82
Lastpage :
87
Abstract :
In multiprocessor systems, the interconnection network design is critical for overall system performance. In this paper, we show the modified hierarchical ring network, called as Torus ring, and deeply evaluate the performance of the Torus ring. The Torus ring has an advantage over the hierarchical ring when the destination of network packet is the adjacent local ring, especially to the backward direction, by exploiting the memory access locality. Further, the performance gain of the Torus ring is expected to increase, due to the spatial locality of the applications and the efficient utilization of link bandwidth. In the simulation results, the overall execution time of Torus ring is reduced, up to 4.5% with moderate ring utilization ratios, compared to the hierarchical ring
Keywords :
hierarchical systems; multiprocessor interconnection networks; network topology; performance evaluation; Torus ring; exploiting link utilization; interconnection network design; memory access locality; modified hierarchical ring; multiprocessor systems; performance evaluation; Analytical models; Bandwidth; Clocks; Large-scale systems; Multiprocessing systems; Multiprocessor interconnection networks; Network topology; Performance gain; Scalability; System performance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing and Information Technology, 2005. Proceedings of the Fifth IEEE International Symposium on
Conference_Location :
Athens
Print_ISBN :
0-7803-9313-9
Type :
conf
DOI :
10.1109/ISSPIT.2005.1577074
Filename :
1577074
Link To Document :
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