Overcoming carbon nanotube variations through co-optimized technology and circuit design

CNT variations substantially degrade CNFET benefits. Our framework for joint exploration and optimization of CNT processing and CNFET circuit design is required to overcome this significant challenge. We present multiple CNT processing routes, which optimize multiple processing parameters together with design techniques, to achieve highly energy-efficient CNFET circuits with minimal impact of variations. Such multiple routes are essential for a successful CNFET technology to avoid potential obstacles. Our framework can be adapted for advanced nodes with proper device models, and also for a wide variety of processing techniques (e.g., CNT sorting [16]).