A unified 3D device simulation of random dopant, interface trap and work function fluctuations on high-к/metal gate device

In this work, we for the first time estimate total fluctuation resulting from random dopants (RDs), interface trap (ITs) and work functions (WKs) using experimentally calibrated 3D device simulation on 16-nm-gate high-k/metal gate devices. The total 3D simulated threshold voltage fluctuation (σV_th), induced by the aforementioned random sources simultaneously, is 55.5 mV for NMOS; however, a statistical total sum of these fluctuations is 12.3% overestimation because independence assumption on random variables is invalid owing to strong interactions among RDs, ITs and WKs. Device´s DC/AC and CMOS SRAM circuit fluctuations have similar observation. FinFET-based structure innovation possessing large fluctuation suppression (σV_th = 30.2 mV; 45.6% reduction), compared with process efforts on planar one, is further discussed.